According to well known prior art IC (integrated circuit) packaging methodologies, semiconductor dice are singulated and mounted using epoxy or other conventional means onto respective die attach pads (attach paddles) of a leadframe strip. Traditional QFP (Quad Flat Pack) packages incorporate inner leads which function as lands for wire bonding the semiconductor die bond pads. These inner leads typically require mold locking features to ensure proper positioning of the leadframe strip during subsequent molding to encapsulate the package. The inner leads terminate in outer leads that are bent down to contact a mother board, thereby limiting the packaging density of such prior art devices.
In order to overcome these and other disadvantages of the prior art, the Applicants previously developed a Leadless Plastic Chip Carrier (LPCC). According to Applicants' LPCC methodology, a leadframe strip is provided for supporting several hundred devices. Singulated IC dice are placed on the strip die attach pads using conventional die mount and epoxy techniques. After curing of the epoxy, the dice are wire bonded to the peripheral internal leads by gold (Au), copper (Cu), aluminum (Al) or doped aluminum wire bonding. The leadframe strip is then molded in plastic or resin using a modified mold wherein the bottom cavity is a flat plate. In the resulting molded package, the die pad and leadframe inner leads are exposed. By exposing the bottom of the die attach pad, mold delamination at the bottom of the die pad is eliminated, thereby increasing the moisture sensitivity performance. Also, thermal performance of the IC package is improved by providing a direct thermal path from the exposed die attach pad to the motherboard. By exposing the leadframe inner leads, the requirement for mold locking features is eliminated and no external lead standoff is necessary, thereby increasing device density and reducing package thickness over prior art methodologies. The exposed inner leadframe leads function as solder pads for motherboard assembly such that less gold wire bonding is required as compared to prior art methodologies, thereby improving electrical performance in terms of board level parasitics and enhancing package design flexibility over prior art packages (i.e. custom trim tools and form tools are not required). These and several other advantages of Applicants' own prior art LPCC process are discussed in Applicants' U.S. Pat. No. 6,229,200, the contents of which are incorporated herein by reference.
In applicant's own U.S. Pat. No. 6,585,905, issued Jul. 1, 2003 and incorporated herein by reference, a process is provided for fabricating a leadless plastic chip carrier in which the semiconductor die sits in a portion of the die attach pad that is reduced in thickness. The leadframe strip is selectively etched to define a pattern for the die attach pad and the contact pads such that a portion of the die attach pad has reduced thickness compared to the thickness of the contact pads. The semiconductor die is mounted in the portion of the die attach pad with reduced thickness, followed by wire bonding and overmolding. This structure provides for several advantages. For example, the package profile can be reduced and the length of the wire bonds from the semiconductor die to the die attach pad and to the contact pads is reduced, thereby reducing electrical impedance in the package. Also, the three-dimensional nature of the die attach pad provides additional exposed metal for adhering to the molding compound, thereby providing a more robust package.
Still further improvements in high performance integrated circuit (IC) packages are driven by industry demands for increased thermal and electrical performance, decreased size and cost of manufacture.